1. Field of the Invention
The present disclosure relates to a method of designing a layout, a design system and a computer program product for a multi-finger complementary metal oxide semiconductor (CMOS) inverter including a multi-finger N-type field effect transistor (NFET) and a multi-finger P-type field effect transistor (PFET). More particularly, a selected layout of common output nodes that are formed on metallization wires, which connect the drain regions of the multi-finger NFET and the drain regions of the multi-finger PFET of the CMOS inverter, respectively, can reduce parasitic drain-node wire resistance without increasing wiring capacitance and thus, maximize output current for the CMOS inverter and to reduce the CMOS inverter's delay.
2. Description of Related Art
Inverters are widely used in circuit design. For example, inverters are used in ring oscillators to benchmark, characterize and compare circuits within an integrated circuit device. Inverters are also used in repeaters to reduce an interconnect's resistance-capacitance (RC) delay. Reducing RC delay is desirable and can be accomplished by reducing the electrical resistance to the total drain currents of the complementary transistors of a CMOS inverter.
Parasitic drain-node resistance greatly impacts semiconductor device performance. Thus, during semiconductor device layout and design, finding ways to minimize parasitic drain node resistance is very important. However, a conventional layout used to connect a multi-finger NFET and a multi-finger PFET can result in a relatively large drain-node wire resistance.
There remains a need to improve the layout design of a multi-finger CMOS inverter, which uses a multi-finger NFET and a multi-finger PFET, to reduce the parasitic drain-node wire resistance and thus, maximize current output of the multi-finger CMOS inverter.